Input stage resistant against high voltage swings

ABSTRACT

An input stage includes a signal input (IN) for receiving an input signal s(t) and a digital input stage ( 15 ) designed for operation at a supply voltage (VDD). The input stage ( 15 ) includes CMOS transistors, which are sensitive to voltages across transistor nodes going beyond a voltage limit (V max ) and an input (IINV). Voltage limiting circuitry (B) is arranged between the signal input (IN) and the input (IINV). The voltage limiting circuitry (B) includes an input switch (ns) controllable by the state of the input signal s(t), and limit voltages at the input (IINV) to the supply voltage (VDD). In addition, over-voltage protection (A) is provided between the signal input (IN) and the supply voltage (VDD). The circuitry for over-voltage protection (A) includes at least one active circuit element arranged so as to mimic part of a zener function.

The present invention relates to input stages having an improvedprotection against voltage swings. In particular, the present inventionrelates to digital input stages and their protection.

While modern CMOS IC (complementary metal oxide semiconductor integratedcircuit) fabrication technologies are going down with criticalgeometrical dimensions, the maximum allowed voltage swing acrossindividual transistors and with it the maximum allowed supply voltage isgoing down rapidly. On the other hand the signal swing at an input portof a CMOS device must for compatibility reasons go beyond these voltagelimits.

A solution to this problem presently is to enhance the CMOS fabricationprocess by processing steps, which allow the fabrication of transistorscapable of working at higher voltage swings. This on one hand requiresadditional and costly fabrication steps and on the other hand calls foran additional supply domain and level shifters to accommodate to thevoltage swing internal to the integrated circuit.

In particular in modern submicron CMOS processes the maximum supplyvoltage V_(DDmax) is determined by reliability considerations forapplication of transistors in standard digital gates. The requirement isthat any voltage difference across transistor nodes does not go beyondcertain limit V_(max). FIG. 1 shows the relevant voltages of ann-channel transistor 1 with V_(GS), V_(DS), V_(GD)<V_(max), for example.For digital gates this requires V_(max) to be the maximum allowed supplyvoltage of the whole chip of which the transistor is a part. Note thatthe voltage towards bulk is not limited to the same extent.

For signal processing this requires the signal swing to stay within thelimits posed by the maximum allowed supply voltage. With supply voltagesgoing down further with the advance of smaller geometry this has asevere impact on the accommodation of signal swings at the input portsof a circuit, which in many cases go beyond V_(max).

A state of the art input stage circuit 2 is illustrated in FIG. 2. Thestandard digital input stage 2 comprises two inverters 11 and 12 beingsupplied by the chip supply voltage V_(DD). Electrostatic discharge(ESD) protection elements R1, D1 and D2 are provided between thecircuit's input pad 3 and the input IINV of the input stage 2. ESDprotection is employed in order to prevent the very sensitive inputstage 2 from being destroyed when it is subjected to a discharge event.This might happen for example when somebody induces a voltage peak intothe circuitry by touching the pins of the chip. In general V_(DD) wouldbe close to V_(max). In case a high voltage input signal going beyondthe limits of V_(max) dictated by the fabrication technology is applied,the voltage at the node IINV would go above the limit, leading todestruction or at least severe life time reduction. Another effect isthat the diode D2 would go into conduction. This would lead to anundesirable static current flow. The input stage 2 of FIG. 2 comprisesstandard transistors ni1, ni2, pi1, and pi2.

As mentioned above, one possible solution to the problem is to addfabrication steps to produce circuit elements which are able towithstand higher voltages. FIG. 3 shows a corresponding example. Aninput stage 4 with ESD protection elements R1, D1 and D2 is shown. Inthis case transistors ni1, ni2, pi1, and pi2 of the input stage 4 arespecial elements being designed to cope with voltages higher thanV_(max) by special and expensive process steps. Note that an additionalsupply domain V_(DDhigh) and a level shifter 5 is required in order toshift the voltages to the lower levels of the V_(DD) voltage domain.

It is an object of the present invention to provide circuits that avoidsor reduces the drawbacks of conventional devices, and to provide devicesbased on such circuits.

It is another object of the present invention to provide devices with animproved resistance against voltage swings at their input.

These and other objects are accomplished by a circuit that comprises asignal input for receiving an input signal, and a digital input stagebeing designed for operation at a supply voltage. The input stagecomprises an input (IINV) and CMOS transistors that are known to besensitive to voltages across transistor nodes going beyond a voltagelimit. Voltage limiting means are arranged between the signal input andthe input (IINV). The voltage limiting means comprise an input switchbeing controllable by the state of the input signal and are employed inorder to limit voltages at the input (IINV) to the supply voltage. Thecircuit further comprises means for over-voltage protection beingsituated between the signal input and the supply voltage. The means forover-voltage protection comprise at least one active circuit elementthat is arranged so as to mimic at least the breakdown part of a zenerfunction.

The present invention allows to realize circuits with reducedfabrication technology costs and less complex system design.

For a more complete description of the present invention and for furtherobjects and advantages thereof, reference is made to the followingdescription, taken in conjunction with the accompanying drawings, inwhich:

FIG. 1 is a schematic representation of a conventional n-channeltransistor;

FIG. 2 is a schematic representation of a standard digital input stage;

FIG. 3 is a schematic representation of a conventional digital inputstage designed to cope with high input voltages;

FIG. 4 is a schematic representation of a first embodiment according tothe present invention;

FIG. 5 is a schematic representation of a second embodiment according tothe present invention;

FIG. 6 is a schematic representation of a third embodiment according tothe present invention;

FIG. 7 is a detailed representation of a fourth embodiment according tothe present invention;

FIG. 8 is a diagram depicting the different voltages at the nodes of acircuit, according to the present invention;

FIG. 9 is another diagram depicting the different voltages at the nodesof a circuit, according to the present invention;

FIG. 10 is another diagram depicting the different voltages at the nodesof a circuit, according to the present invention;

FIG. 11 is another diagram depicting the different voltages at the nodesof a circuit, according to the present invention.

A first embodiment is illustrated in FIG. 4. A circuit 10 is shown thatcomprises a signal input 11 (IN) for receiving a digital input signals(t), and a digital input stage 15 being designed for operation at asupply voltage V_(DD). The input stage 15 comprises several CMOStransistors and an input IINV. These transistors are sensitive tovoltages across their nodes going beyond a voltage limit V_(max). Inorder to protect the digital input stage 15 against high voltage swingsat the signal input 11 (IN), voltage limiting means 14 (B) are arrangedbetween the signal input 11 (IN) and the input IINV. The voltagelimiting means 14 (B) limit the voltages at the input IINV to the supplyvoltage V_(DD). In order to be able to achieve this, the voltagelimiting means 14 (B) comprise an input switch (ns) being controllableby the state of the input signal s(t). In addition to the voltagelimiting means 14 (B), the circuit 10 comprises means for over-voltageprotection 12 (A) being situated between the signal input 11 (IN) andthe supply voltage (V_(DD)). The means for over-voltage protection 12(A) comprise at least one active circuit element being arranged so as tomimic at least the breakdown part of a zener function. I.e., the meansfor over-voltage protection 12 (A) at least partially operate like azener diode.

The circuit 10 may also comprise an input protection diode 13 (D1) beingsituated between the input node (IN0) and ground, as depicted in FIG. 4.

Another embodiment is illustrated in FIG. 5. The circuit 20 in FIG. 5comprises a digital input stage 25 having an input IINV and an outputOUT. Like in FIG. 4, the circuit 20 comprises means for over-voltageprotection 22 (A) and voltage limiting means 24 (B). In order to furtherimprove the protection of the input stage 25, means 27 (D) forprotection against static currents are provided. The means 27 (D) forprotection against static currents provide for a positive feedbackpulling the input IINV of the input stage 25 up to the supply voltageV_(DD) in order to prevent static (through) currents from flowingthrough part of the input stage's elements. The means 27 (D) forprotection against static currents may comprise a p-type CMOStransistor, for example.

The circuit 20 may further comprise speed boost means 26 (C) having atleast one capacitive element (Cb). The speed boost means 26 (C) allowthe turn-on/turn-off behavior of the voltage limiting means 24 (B) to beaccelerated. The charging of the capacitive element (Cb) depends on thestate of a signal derived from the input signal s(t) such that thecapacitive element (Cb) is charged to the supply voltage V_(DD) if theinput signal s(t) is low. As schematically illustrated in FIG. 5, thespeed boost means 26 (C) together with the voltage limiting means 24 (B)may form one functional unit.

The optional means 27 (D) for protection against static currents areemployed to limit static through currents. Such a through currenttypically occurs when the voltage at the node IINV is lower than thesupply voltage V_(DD), since the different voltages lead to a voltagedifference across the digital input stage.

Yet another embodiment is depicted in FIG. 6. The circuit 30 iscomparable to the one depicted in FIG. 5. Hence identical elements carrythe same reference numbers as in FIG. 5. The circuit 30 comprises acurrent limiting resistor R1 being situated between the signal input 21(IN) and the input node IN0. A resistor Rz is situated between the meansfor over-voltage protection 22 (A) and the supply voltage V_(DD).

In another embodiment, the active circuit element being part of themeans for over-voltage protection (A) is a transistor. This transistoris arranged such that during normal operation it does not enterconductive state. Preferably, the means for over-voltage protection (A)comprise a plurality of transistors, preferably n-channel CMOStransistors (nz1, nz2, nz3), or p-channel CMOS transistors, or bipolartransistors, and a resistor Rz.

In an advantageous embodiment, the means (D) for protection againststatic currents provide for a positive feedback pulling the voltage atthe input IINV up to the supply voltage V_(DD) in order to prevent thestatic currents from flowing through part of the elements of the digitalinput stage. The means (D) for protection against static currents mayfor example comprise a p-type CMOS transistor (pp2) serving as keepertransistor.

In yet another embodiment, the switch of the voltage limiting means (B)may be an n-channel CMOS transistor (ns). The voltage limiting means (B)may further comprise a p-channel CMOS transistor (pp1) for controllingthe voltage at the gate node (GNS) of the n-channel CMOS transistor(ns). According to the present invention, the node GNS is a switchednode.

The means for over-voltage protection (A) may be designed so that theyabsorb destructive voltages when the supply voltage V_(DD) is zero.

Another embodiment is illustrated in FIG. 7. As illustrated in thisFigure, the circuit 40 comprises a digital input stage 45 with twoinverters I1 and I2. The inverter I1 comprises a p-channel transistorpi1 and an n-channel transistor ni1, and the inverter I2 comprises ap-channel transistor pi2 and an n-channel transistor ni2. FIG. 7 furthershows a proposal for elements being able to cope with high input swingsusing only standard elements. As a first step, the usual protectiondiode D2 to V_(DD) (see FIG. 2 or 3, for example) is removed to avoidstatic current through this element. It is well proven practice that asingle diode D1 with a current limiting resistor R1 sufficientlyprotects the digital input stage 45 from ESD damage. An input n-channelswitch ns is provided, which limits the voltage at node the IINV toV_(DD) and which takes the rest of voltage going beyond V_(DD) thusleading to the circuit 40 being able to cope with an input swing s(t),which is twice V_(DD). For V_(DD)=V_(max) this is 2*V_(max). In order tobe able to control the gate of the n-channel switch transistor ns at thenode GNS, a bootstrap structure comprising a p-channel transistor pp1and a bootstrap capacitor Cb is used with the following functionality:If the input signal s(t) at node IN is low, the capacitor Cb is chargedto V_(DD) at node GNS via the p-channel transistor pp1 and the n-channelswitch transistor ns is conducting, thus transferring the input voltageat the node IN to the node IINV. On a rising edge of the input signals(t), node IN0 goes high turning off the p-channel transistor pp1 andthe node IN1 goes high pushing GNS high to keep the n-channel switchtransistor ns in conduction. Thus the input state at IN is transferredto the node IINV, but limited in swing by the n-channel switchtransistor ns. Any excessive voltage at the node GNS is discharged viathe p-channel transistor pp1 to V_(DD) by the p-channel transistor pp1going into reverse conduction. In this way, the voltage at the node GNSis limited to one p-channel transistor threshold voltage above V_(DD).If the capacitor Cb loses charge over a longer period of time, the nodeIINV is still kept at the proper voltage by a keeper transistor pp2,which also limits the voltage at the node IINV to V_(DD). In order toallow the p-channel transistor pp1 to be switched off with propertiming, a resistor R2 may be employed that slightly delays the inputsignal at the node IN1. In case the sequence at the input IN starts witha high voltage after power-up, the sequence starts with the firstfalling edge on IN. Of course the circuit 40 shall also be operatingwith a standard input swing between 0 and V_(DD). This requires thefirst inverter ni1/pi1 of the input stage 45 to be rationed in such away, that it is able to cope with a high level below V_(DD). By positivefeedback via the transistor pp2, the voltage at the node IINV is finallypulled to V_(DD).

In case a high level voltage is applied while the supply voltage V_(DD)is still turned off (a situation which might occur in battery operatedsystems with elaborate power management), the input is clamped to a safevalue via the means for over-voltage protection 22 (A). The means forover-voltage protection 22 (A) may comprise n-channel devices nz1 to nz3and a resistor Rz, as illustrated in FIG. 7. In normal operation then-channel devices nz1 to nz3 will not be conducting, but for V_(DD)=0they absorb destructive voltages. The means for over-voltage protection22 (A) may be comprised of any combination of n-channel, p-channel orbipolar diodes.

The operation of the circuit 40 depicted in FIG. 7 is explained inconnection with the diagrams given in FIGS. 8–11. In all these examples,the supply voltage V_(DD)=V_(max) is set to 1 Volt. In FIGS. 8 and 9 thesignal swing of the signal s(t) is 2 Volts.

In FIG. 8 a situation is shown, where the signal sequence s(t) starts ata low level at about 0 Volt at t=0. The signal at the node GNS almostfollows the signal s(t). It shows a peak at the falling edge of thesignal s(t) that almost goes back to 0 Volt. The circuit blocks A, B, C,and D provide for a voltage x(t) at the node IINV that closely followsthe signal s(t) at the input IN. As illustrated in FIG. 8, the maximumvoltage of x(t) is at about V_(DD)=1 Volt. The edges are somewhatrounded. Finally, the output signal y(t) at the output OUT of thedigital input stage 45 are a copy of the signal s(t) with the maximumswing being limited to about V_(DD)=1 Volt.

In FIG. 9 a situation is shown, where the signal sequence s(t) startswith a high level at about 2 Volts at t=0. The signal at the node GNSslowly builds up before it more or less follows the signal s(t). Thecircuit blocks A, B, C, and D provide for a voltage x(t) at the nodeIINV that after some delay (in the present example the delay is about250 ns, but only for the first pulse after power-up) closely follows thesignal s(t) at the input IN. As illustrated in FIG. 9, the maximumvoltage of x(t) is at about V_(DD)=1 Volt. The edges are somewhatrounded. Finally, the output signal y(t) at the output OUT of thedigital input stage 45 are a copy of the signal s(t) with the maximumswing being limited to about V_(DD)=1 Volt. The signal y(t) is alsodelayed.

FIGS. 10 and 11 are given to illustrate that the whole circuit 40 isalso fully functional when the signal swing of the signal s(t) is low.In the present examples, the signal swing of s(t) remains below 1 Volt.In FIG. 10 a situation is depicted where s(t) starts with a low level att=0. In FIG. 11 the signal s(t) starts at a high level of about 1 Voltat t=0. In both situations, the output signals y(t) at the output OUT ofthe digital input stage 45 are copies of the signals s(t) with themaximum swing being limited to about V_(DD)=1 Volt. Note that the signaly(t) in FIG. 11 is also delayed.

Various circuits are presented herein, which allow digital input pads tocomply with voltages up to 2 times the maximum allowed voltage acrossone transistor for a given fabrication technology. According to thepresent invention, standard devices are employed without the need for:

-   -   an additional high voltage supply domain,    -   a level shifter to bridge the two supply domains,    -   additional fabrication process steps, to provide transistors,        which withstand high voltages.

Additionally a protection element (A) is presented, which absorbsdestructive voltages, when the supply voltage is turned off.

The present scheme can be used to protect CMOS (complementary metaloxide semiconductor) and BiCMOS circuits (bipolar devices combined withCMOS subcircuits on a single chip), for example.

In the drawings and specification there has been set forth preferredembodiments of the invention and, although specific terms are used, thedescription thus given uses terminology in a generic and descriptivesense only and not for purposes of limitation.

1. A circuit comprising: signal input (IN) for receiving an input signal(s(t)), a digital input stage (15) being designed for operation at asupply voltage (VDD), the digital input stage (15) comprising: CMOStransistors sensitive to voltages across transistor nodes going beyond avoltage limit (V_(max)) an input (IINV), voltage limiting means (B)being arranged between the signal input (IN) and the input (IINV) forlimiting voltages at the input (IINV) to the supply voltage (VDD), thevoltage limiting means (B) comprising: an input switch (ns) beingcontrollable by the state of the input signal (s(t)), means forover-voltage protection (A) being situated between the signal input (IN)and the supply voltage (VDD), the means for over-voltage protection (A)comprising at least one active circuit element which functions so as tomimic at least a breakdown part of a zener function, and speed boostmeans (C) having at least one capacitive element (Cb) speeding up theturn-on/turn-off behavior of the input switch (ns).
 2. The circuit ofclaim 1, wherein the element is a transistor being arranged such thatduring normal operation the transistor does not enter conductive state.3. The circuit of claim 1 or 2, wherein the transistor of the means forover-voltage protection (A) includes at least one of an n-channel MOStransistor (nz1, nz2, nz3), a p-channel MOS transistor, and a bipolartransistor, and the means for over-voltage protection (A) furthercomprises a resistor (Rz).
 4. The circuit of claim 1 or 2, furthercomprising a current limiting resistor (R1) being situated between thesignal input (IN) and an input node (IN0), and an input protection diode(D1) being situated between the input node (IN0) and ground.
 5. Thecircuit of claim 1 or 2, further comprising means (D) for protectionagainst static currents.
 6. The circuit of claim 5, wherein the means(D) for protection against static currents provide for a positivefeedback pulling the input (IINV) up to the supply voltage (VDD) inorder to prevent the static currents from flowing through part (pi1,ni1) of the input stage (15).
 7. The circuit of claim 5, wherein themeans (D) for protection against static currents comprise a p-type CMOStransistor (pp2) serving as keeper transistor.
 8. The circuit of claim1, wherein the charging of the capacitive element (Cb) depends on thestate of a signal derived, from the input signal (s(t)).
 9. The circuitof claim 8, wherein the capacitive element (Cb) is charged to the supplyvoltage (Vdd) if the input signal (s(t)) is low.
 10. The circuit ofclaim 1 or 2, wherein the input switch is an n-channel MOS transistor(ns).
 11. The circuit of claim 1 or 2, wherein the means forover-voltage protection (A) absorb destructive voltages when the supplyvoltage (VDD) is zero.
 12. Circuit according to claim 1 or 2 being madeusing a submicron fabrication process, preferably a deep submicronfabrication process.
 13. A circuit comprising: signal input (IN) forreceiving an input signal (s(t)), a digital input stage (15) beingdesigned for operation at a supply voltage (VDD), the digital inputstage (15) comprising: CMOS transistors sensitive to voltages acrosstransistor nodes going beyond a voltage limit (Vmax), an input (IINV),voltage limiting means (B) being arranged between the signal input (IN)and the input (IINV) for limiting voltages at the input (IINV) to thesupply voltage (VDD), the voltage limiting means (B) comprising: aninput switch (ns) being controllable by the state of the input signal(s(t)), means for over-voltage protection (A) being situated between thesignal input (IN) and the supply voltage (VDD), the means forover-voltage protection (A) comprising at least one active circuitelement which functions so as to mimic at least a breakdown part of azener function, wherein the input switch is an n-channel MOS transistor(ns), and wherein the voltage limiting means (B) further comprise ap-channel MOS transistor (pp1) for controlling the voltage at the gatenode (GNS) of the n-channel MOS transistor (ns).